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16 Mbit SPI Serial Flash
SST25VF016B
Data Sheet
SST25VF016B16Mb Serial Peripheral Interface (SPI) flash memory
FEATURES:
•
Single Voltage Read and Write Operations
– 2.7-3.6V
Auto Address Increment (AAI) Programming
– Decrease total chip programming time over
Byte-Program operations
Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin in AAI Mode
High Speed Clock Frequency
– Up to 80 MHz
Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
Low Power Consumption:
– Active Read Current: 10 mA (typical)
– Standby Current: 5 µA (typical)
Software Write Protection
– Write protection through Block-Protection bits in
status register
Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
Packages Available
– 8-lead SOIC (200 mils)
– 8-contact WSON (6mm x 5mm)
All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
SST’s 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ultimately
lowers total system costs. The SST25VF016B devices are
enhanced with improved operating frequency and even
lower power consumption than the original SST25VFxxxA
devices. SST25VF016B SPI serial flash memories are
manufactured with SST’s proprietary, high-performance
CMOS SuperFlash technology. The split-gate cell design
and thick-oxide tunneling injector attain better reliability and
manufacturability compared with alternate approaches.
The SST25VF016B devices significantly improve perfor-
mance and reliability, while lowering power consumption.
The devices write (Program or Erase) with a single power
supply of 2.7-3.6V for SST25VF016B. The total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash memory technologies.
The SST25VF016B device is offered in both 8-lead SOIC
(200 mils) and 8-contact WSON (6mm x 5mm) packages.
See Figure 2 for pin assignments.
©2008 Silicon Storage Technology, Inc.
S71271-03-000
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
9/08
1
16 Mbit SPI Serial Flash
SST25VF016B
Data Sheet
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
CE#
SCK
SI
SO
WP#
HOLD#
1271 B1.0
FIGURE
1: Functional block Diagram
©2008 Silicon Storage Technology, Inc.
S71271-03-000
9/08
2
16 Mbit SPI Serial Flash
SST25VF016B
Data Sheet
PIN DESCRIPTION
CE#
V
DD
1
8
CE#
V
DD
1
8
SO
HOLD#
2
7
SO
HOLD#
2
7
Top View
To p V i e w
WP#
SCK
WP#
3
6
SCK
3
6
V
SS
SI
V
SS
4
5
SI
4
5
1271 08-wson QA P2.0
1271 08-soic S2A P1.0
8-lead SOIC
8-Contact WSON
FIGURE
2: Pin Assignments
TABLE
1: Pin Description
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
Outputs Flash busy status during AAI Programming when reconfigured as RY/BY# pin.
See “Hardware End-of-Write Detection” on page 12 for details.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
Hold
To temporarily stop serial communication with SPI flash memory without resetting the
device.
V
DD
Power Supply
To provide power supply voltage:
2.7-3.6V for SST25VF016B
V
SS
Ground
T1.0 1271
©2008 Silicon Storage Technology, Inc.
S71271-03-000
9/08
3
16 Mbit SPI Serial Flash
SST25VF016B
Data Sheet
MEMORY ORGANIZATION
The SST25VF016B SuperFlash memory array is orga-
nized in uniform 4 KByte erasable sectors with 32 KByte
overlay blocks and 64 KByte overlay erasable blocks.
The SST25VF016B supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 3, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25VF016B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
CE#
MODE 3
MODE 3
MODE 0
MODE 0
SCK
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
DON'T CARE
SI
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
1271 SPIprot.0
FIGURE
3: SPI Protocol
©2008 Silicon Storage Technology, Inc.
S71271-03-000
9/08
4
16 Mbit SPI Serial Flash
SST25VF016B
Data Sheet
Hold Operation
The HOLD# pin is used to pause a serial sequence under-
way with the SPI flash memory without resetting the clock-
ing sequence. To activate the HOLD# mode, CE# must be
in active low state. The HOLD# mode begins when the
SCK active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
coincide with the SCK active low state, then the device
exits in Hold mode when the SCK next reaches the active
low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-
impedance state while SI and SCK can be V
IL
or V
IH.
If CE# is driven active high during a Hold condition, it resets
the internal logic of the device. As long as HOLD# signal is
low, the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
24 for Hold timing.
SCK
HOLD#
Active
Hold
Active
Hold
Active
1271 HoldCond.0
FIGURE
4: Hold Condition Waveform
Write Protection
SST25VF016B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP3, BP2, BP1, BP0, and BPL) in the status register pro-
vide Write protection to the memory array and the status
register. See Table 4 for the Block-Protection description.
TABLE
2: Conditions to execute Write-Status-
Register (WRSR) Instruction
WP#
BPL
Execute WRSR Instruction
L
1
Not Allowed
L
0
Allowed
H
X
Allowed
T2.0 1271
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down func-
tion of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 2). When WP# is high, the lock-down func-
tion of the BPL bit is disabled.
©2008 Silicon Storage Technology, Inc.
S71271-03-000
9/08
5
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