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Power Management
Texas Instruments Incorporated
Simultaneous power-down sequencing with
the TPS74x01 family of linear regulators
By Jeff Falin
Senior Applications Engineer
Introduction
In the past, ensuring successful power up
for DSPs and FPGAs in electronic equip-
ment was a challenge. The most recent
DSPs and FPGAs have more relaxed
requirements for core and I/O power
up/down. However, a few still specify
power-up ramp rates and recommend
sequential sequencing for predictable and
repeatable startup. Even fewer specify
power-down requirements, including ramp
rates and/or sequences. In most cases, the
ultimate goal of these requirements is to
ensure that the DSP and FPGA power rails
do not have a larger differential voltage
than that for which they were designed,
even during the brief periods at power
up/down. Otherwise, immediate or cumula-
tive damage to internal circuits, which
reduces long-term reliability, can occur.
Therefore, the ideal method for DSP and
FPGA power up/down is for all rails to rise
and fall at the same time and rate.
Two or more power-rail ICs are said to
have been simultaneously sequenced on
power up when they track one another with
the same rising dv/dt, and the lower rail
stops at its regulated voltage while the
upper rail continues to its higher regulated
voltage. Various devices, including the
TPS74301 linear regulator, have a tracking
input to provide simultaneous power-up
sequencing. Simultaneous sequencing on
power up/down is implemented by replac-
ing the converter’s error-amplifier reference
voltage with the tracking input signal while
the signal is less than the reference voltage.
However, for power-down sequencing to
work, the converter must have circuitry to
pull down the output under light load.
Switching converters such as the TPS54x80
family can easily pull down the output by modulating the
duty cycle. Most linear regulators do not have pull-down
circuitry; so, even though the linear regulator tries to
lower the output voltage, it must wait for the output
Figure 1. Block diagram of TPS74301 providing
power-up/down sequencing
5V
V IN
PH
3.3 V
C O1
TPS54610
EN
66 µF
V SENSE
GND
SS/ENA
R L1
332
3.74 k
V IN
PH
1.8 V
TPS54680
6 6 µF
TRACKIN
V SENSE
GND
9 .76 k
10 k
8.66 k
V IN
TRACK
V OUT
1.5 V
1.0
µF
C O2
TPS74301
4.12 k
330 µF
EN
VBIAS
FB
4.7
µF
GND
R L2
4.75 k
Pull-Down Circuitry
R PD
5V
10 k
7.5
Q2
100 k
Q1
capacitor to discharge through the load resistance. Figure 1
shows a block diagram of the TPS74301 configured to
track the 3.3-V rail from a TPS54610. See Reference 1
for a complete schematic of TPS54xxx devices.
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Analog Applications Journal
High-Performance Analog Products
3Q 2007
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Texas Instruments Incorporated
Power Management
Figure 2 shows simultaneous power up of the 3.3-V and
1.5-V rails. Figure 3 shows that, with the pull-down
circuitry (low-cost, bipolar transistors Q1 and Q2 and their
supporting components) removed, the TPS74301 output
voltage does not track down because the power-down load
resistance is too high. The pull-down circuitry shown in
Figure 1 adds the pull-down resistor, R PD , in parallel with
R L2 , which lowers the regulator’s load resistance and its
RC time constant (R L2 ×
C O2 ) during power down. This
means that the TPS74301 output will track down as shown
in Figure 4, since the R PD || (R L2 ×
C O2 ) time constant is
less than the R L1 × C O1 time constant.
Figure 2. TPS74301 1.5-V output with
power-up sequencing
Figure 3. TPS74301 1.5-V output without
power-down sequencing
3.3 V (500 mV/div)
3.3 V (500 mV/div)
EN (1 V/div)
1.8 V (500 mV/div)
1.8 V ( 500 mV/div )
EN ( 1 V/div )
1.5 V ( 500 mV/div )
1.5 V (500 mV/div)
Timebase (1 ms/div)
Timebase (10 ms/div)
Figure 4. TPS74301 1.5-V output with
power-down sequencing
3.3 V (500 mV/div)
EN ( 1 V/div )
1.8 V ( 500 mV/div )
1.5 V ( 500 mV/div )
Timebase (5 ms/div)
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Analog Applications Journal
3Q 2007
High-Performance Analog Products
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Power Management
Texas Instruments Incorporated
The circuit in Figure 5 shows how to
make all versions of the TPS74x01 family
achieve “pseudo” simultaneous power-
up/down sequencing by having V OUT follow
V IN . When V IN is less than the sum of the
output voltage and the regulator’s dropout
voltage (V DO ) for a given output load, the
regulator’s pass element is operating in
dropout. Therefore, if the load during
power up/down is heavy enough, the regu-
lator’s output voltage could be below the
voltage being tracked by V DO(max) . Note that
the soft-start capacitor, C SS , must be set so
that the TPS74x01 output ramps up faster
than V IN .
Figures 6 and 7 show power-up/down
sequencing using the nontracking TPS74801
and TPS74201, respectively, with a 1.5-A
output load and V OUT = 1.5 V. Since the
TPS74801 has a higher dropout than the
TPS74201, the difference between V OUT =
1.5 V and V IN = 1.8 V is more noticeable in
Figure 6 than in Figure 7. Figures 8 and 9
show the same results but with no load con-
nected to the output and with V OUT = 1.5 V.
Notice in Figures 8b and 9b that on power
down the output voltage stays high for a
brief time (creating a ledge of sorts) until
the pass element’s reverse diode turns on to
assist in discharging the output capacitance.
Figure 5. Block diagram of TPS74x01 providing pseudo
power-up/down sequencing
5V
V IN
PH
3.3 V
C O1
TPS54610
66 µF
SS/ENA
FB
R L1
332 Ω
10 k Ω
V IN
PH
1.8 V
TPS54680
6 6 µF
TRACKIN
FB
GND
9 .76 k Ω
1.0 µ F
V IN
V OUT
1.5 V
C O2
TPS74x01
4.12 k Ω
330 µF
VBIAS
FB
SS
GND
R L2
4.75 k
Ω
4.7 µF
C SS
Figure 6. TPS74801 1.5-V output with R L2
= 1 Ω
3.3 V (500 mV/div)
3.3 V ( 500 mV/div )
EN ( 1 V/div )
EN ( 1 V/div )
1.8 V ( 500 mV/div )
1.8 V (500 mV/div)
1.5 V ( 500 mV/div )
1.5 V
(500 mV/div)
Timebase (500 µs/div)
Timebase (2 ms/div)
(a)
Pseudo power-up sequencing with V IN connected to
1.8-V output
(b)
Pseudo power-down sequencing with V IN connected to
1.8-V output
22
Analog Applications Journal
High-Performance Analog Products
3Q 2007
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Texas Instruments Incorporated
Power Management
Figure 7. TPS74201 1.5-V output with R L2
= 1 Ω
3.3 V ( 500 mV/div )
3.3 V ( 500 mV/div )
EN ( 1 V/div )
1.8 V (500 mV/div)
EN (1 V/div)
1.8 V ( 500 mV/div )
1.5 V
( 500 mV/div )
1.5 V ( 500 mV/div )
Timebase (1 ms/div)
Timebase (2 ms/div)
(a)
Pseudo power-up sequencing with V IN connected to
1.8-V output
(b)
Pseudo power-down sequencing with V IN connected to
1.8-V output
Figure 8. TPS74801 1.5-V output with no load
3.3 V (500 mV/div)
3.3 V ( 500 mV/div )
EN (1 V/div)
EN ( 1 V/div )
1.8 V (500 mV/div)
1.8 V (500 mV/div)
1.5 V ( 500 mV/div )
1.5 V
( 500 mV/div )
Timebase (500 µs/div)
Timebase (2 ms/div)
(a)
Pseudo power-up sequencing with V IN connected to
1.8-V output
(b)
Pseudo power-down sequencing with V IN connected to
1.8-V output
23
Analog Applications Journal
3Q 2007
High-Performance Analog Products
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Power Management
Texas Instruments Incorporated
Figure 9. TPS74201 1.5-V output with no load
3.3 V (500 mV/div)
3.3 V (500 mV/div)
EN ( 1 V/div )
1.8 V ( 500 mV/div )
EN ( 1 V/div )
1.8 V ( 500 mV/div )
1.5 V ( 500 mV/div )
1.5 V
( 500 mV/div )
Timebase (1 ms/div)
Timebase (2 ms/div)
(a)
Pseudo power-up sequencing with V IN connected to
1.8-V output
(b)
Pseudo power-down sequencing with V IN connected to
1.8-V output
Conclusion
To meet DSP and FPGA power-on requirements, many
new DC/DC converters provide methods for controlling
startup. Some also have integrated features to assist with
those few DSPs and FPGAs that have power-down
requirements. The TPS74x01 family of linear regulators
easily provides simultaneous power-up sequencing and,
with the assistance of simple pull-down circuitry and/or
careful sizing of the load resistance at power down, pro-
vides two different methods for achieving simultaneous
power-down sequencing.
Reference
For more information related to this article, you can down-
load an Acrobat Reader file at www-s.ti.com/sc/techlit/
litnumber and replace “litnumber” with the TI Lit. # for
the materials listed below.
Document Title
TI Lit. #
1. “TPS54680EVM-228 6-Amp,
TPS54880EVM-228 8-Amp, SWIFT™
Regulator Evaluation Module,” User’s Guide . . .slvu077
Related Web sites
www.ti.com/sc/device/ partnumber
Replace partnumber with TPS54610, TPS54680,
24
Analog Applications Journal
High-Performance Analog Products
3Q 2007
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Zgłoś jeśli naruszono regulamin